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ds07-13745-1e fujitsu semiconductor data sheet copyright?2007 fujitsu li mited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 16-bit microcontroller cmos f 2 mc-16lx mb90925 series mb90f927/f927s/v925-101/v925-102 description mb90925 series is a 16-bit general-p urpose high-capacity microcontroller designed for vehicle meter control applications etc. the instruction set retains the same at architecture as f 2 mc-8l and f 2 mc-16l series, with further refinements including high-level language instructions, expanded addressing mode, enhanced signed multiplication and division computation and bit processing. in addition, a 32-bit accumulator is bu ilt in to enable long word processing. note : f 2 mc is the abbreviation of fuji tsu flexible microcontroller. features clock built-in pll clock frequency multiplication circuit. selection of machine clocks (pll clocks) is allowe d among frequency division by 2 on oscillation clock and multiplication of 1 to 4 times of oscillation cloc k(for 4 mhz oscillation clock, 4 mhz to 16 mhz). operation by sub clock(up to 50 khz : 100 khz oscillation clock divided by 2). (continued)
mb90925 series 2 16-bit input capture (4 channels) detects rising, falling, or both edges. 16-bit capture register 4 pin input edge detection latches the 16 -bit free-run timer counter value, and generates an interrupt request. 16-bit reload timer (2 channels) 16-bit reload timer operation (selec t toggle output or one-shot output) event count function selection provided real time watch timer (main clock) operates directly from oscillator clock. interrupt can be generated by second/minute/hour/date counter overflow. 16-bit ppg (3 channels) output pins (3 channels) , exter nal trigger input pin (1 channel) output clock frequencies : f cp , f cp /2 2 , f cp /2 4 , f cp /2 6 delay interrupt generates interrupt for task switching. interrupts to cpu can be generate d/deleted by software setting. external interrupts (8 channels) 8-channel independent operation interrupt source setting available : ?l? to ?h ? edge/ ?h? to ?l? edge/ ?l? level/ ?h? level. a/d converter 10-bit or 8-bit resolution 8 channels (input multiplexed) conversion time : 2.6 s (at f cp = 16 mhz) external trigger startup available (p50/int0/adtg) internal timer startup available (16-bit reload timer 1) uart(lin/sci) (2 channels) equipped with full duplex double buffer clock-asynchronous or clock-synchronous serial transfer is available sio (1 channel) clock synchronized data transmission. lsb-first or msb-first data transfer selection is available. can interface conforms to can specificatio ns version 2.0 part a and b. automatic resend in case of error. automatic transfer in response to remote frame. 16 prioritized message buffers for data and id multiple message support receiving filter has flexible configuration : fu ll bit compare/full bit mask/two partial bit masks supports up to 1 mbps can wakeup function (connects rx internally to int0) lcd controller/driver (32 segment x 4 common) segment driver and command driver with di rect lcd panel (display) drive capability low voltage/program looping detect reset automatic reset when low voltage is detected program looping detection function (continued)
mb90925 series 3 (continued) stepping motor controller (4 channels) high current output for each channel 4 synchronized 8/10-bit pwm for each channel 2 sound generator 8-bit pwm signal mixed with tone frequency from 8-bit reload counter. pwm frequencies : 62.5 khz, 31.2 khz, 15.6 khz, 7.8 khz (at f cp = 16 mhz) tone frequencies : 1/2 pwm frequency, divided by (reload frequency + 1) input/output ports general-purpose input/output port (cmos output) - 70 ports (dual clock system) - 72 ports (single clock system) input level select function for port automotive/cmos-schmitt (initial level is automotive in single chip mode) flash memory security function protect the content of flash memory (flash memory product only)
mb90925 series 4 product lineup mb90f927 mb90f927s mb90v925-101 mb90v925-102 type flash memory product evaluation product cpu f 2 mc-16lx cpu system clock pll clock multiplier circuit ( 1, 2, 3, 4, 1/2 when pll stopped) minimum instruction execution time 62.5 ns (with 4 mhz oscillation clock 4) sub clock pin (x0a, x1a) yes no yes rom flash memory 64 kbytes external ram 4 kbytes 13.5 kbytes i/o port 70 ports 72 ports 70 ports sio 1 channel lcd segment 32 uart uart(lin/sci) 2 channels can interface 1 channel 16-bit input capture 4 channels 16-bit reload timer 2 channels 16-bit free-run timer 1 channel real time watch timer 1 channel 16-bit ppg 3 channels external interrupt 8 channels 8/10-bit a/d converter 8 channels lvd/cpu loop reset yes no stepping motor controller 4 channels sound generator 1 channel flash memory security yes no operation voltage 3.7 v to 5.5 v 4.5 v to 5.5 v packages qfp-100 , lqfp-100 pga-299 part number parameter
mb90925 series 5 pin assignments (top view) (fpt-100p-m06) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 com2 com3 p22/seg0 p23/seg1 p24/seg2 p25/seg3 p26/seg4 p27/seg5 p30/seg6 p31/seg7 v ss p32/seg8 p33/seg9 p34/seg10 p35/seg11 p36/seg12 p37/seg13 p40/seg14 p41/seg15 p42/seg16 p43/seg17 p44/seg18 v cc p45/seg19 p46/seg20 p47/seg21 c p90/seg22 p91/seg23 v0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p92/x0a p93/x1a p57/sga rst p56/sgo/frck p55/rx0 p54/tx0 dv ss p87/pwm2m3 p86/pwm2p3 p85/pwm1m3 p84/pwm1p3 dv cc p83/pwm2m2 p82/pwm2p2 p81/pwm1m2 p80/pwm1p2 dv ss p77/pwm2m1 p76/pwm2p1 p75/pwm1m1 p74/pwm1p1 dv cc p73/pwm2m0 p72/pwm2p0 p71/pwm1m0 p70/pwm1p0 dv ss p53/int3/sck md2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 com1 com0 p15/in0 p14/in1 p13/in2 p12/tin0/in3 p11/tot0 p10/ppg2 p07/ppg1/tin1/seg31 p06/ppg0/tot1/seg30 p05/sck1/trg/seg29 p04/sot1/seg28 p03/sin1/int7/seg27 p02/sck0/int6/seg26 p01/sot0/int5/seg25 p00/sin0/int4/seg24 v cc x1 x0 v ss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 v1 v2 v3 av cc avrh p50/int0/adtg av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p51/int1/si p52/int2/so md0 md1
mb90925 series 6 (top view) (fpt-100p-m05) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p22/seg0 p23/seg1 p24/seg2 p25/seg3 p26/seg4 p27/seg5 p30/seg6 p31/seg7 v ss p32/seg8 p33/seg9 p34/seg10 p35/seg11 p36/seg12 p37/seg13 p40/seg14 p41/seg15 p42/seg16 p43/seg17 p44/seg18 v cc p45/seg19 p46/seg20 p47/seg21 c 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rst p56/sgo/frck p55/rx0 p54/tx0 dv ss p87/pwm2m3 p86/pwm2p3 p85/pwm1m3 p84/pwm1p3 dv cc p83/pwm2m2 p82/pwm2p2 p81/pwm1m2 p80/pwm1p2 dv ss p77/pwm2m1 p76/pwm2p1 p75/pwm1m1 p74/pwm1p1 dv cc p73/pwm2m0 p72/pwm2p0 p71/pwm1m0 p70/pwm1p0 dv ss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p90/seg22 p91/seg23 v0 v1 v2 v3 av cc avrh p50/int0/adtg av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p51/int1/si p52/int2/so md0 md1 md2 p53/int3/sck com3 com2 com1 com0 p15/in0 p14/in1 p13/in2 p12/tin0/in3 p11/tot0 p10/ppg2 p07/ppg1/tin1/seg31 p06/ppg0/tot1/seg30 p05/sck1/trg/seg29 p04/sot1/seg28 p03/sin1/int7/seg27 p02/sck0/int6/seg26 p01/sot0/int5/seg25 p00/sin0/int4/seg24 v cc x1 x0 v ss p92/x0a p93/x1a p57/sga
mb90925 series 7 pin descriptions (continued) pin no. pin name i/o circuit type* 3 function lqfp* 1 qfp* 2 80 82 x0 a high speed oscillator input pin 81 83 x1 high speed oscillator output pin 78 80 p92 g general-purpose i/o port x0a a low speed oscillator input pin. if no oscillator is connected, apply pull-down processing. 77 79 p93 g general-purpose i/o port x1a a low speed oscillator output pin. if no oscillator is connected, leave open. 75 77 rst b reset input pin 83 85 p00 j general-purpose input/output port sin0 uart ch.0 serial data input pin int4 int4 external interrupt input pin seg24 lcd controller/driver segment output 84 86 p01 e general-purpose input/output port sot0 uart ch.0 serial data output pin int5 int5 external interrupt input pin seg25 lcd controller/driver segment output 85 87 p02 e general-purpose input/output port sck0 uart ch.0 serial clock input/output pin int6 int6 external interrupt input pin seg26 lcd controller/driver segment output 86 88 p03 j general-purpose input/output port sin1 uart ch.1 serial data input pin int7 int7 external interrupt input pin seg27 lcd controller/driver segment output 87 89 p04 e general-purpose input/output port sot1 uart ch.1 serial data output pin seg28 lcd controller/driver segment output 88 90 p05 e general-purpose input/output port sck1 uart ch.1 serial clock input/output pin trg 16-bit ppg ch.0 to ch.2 external trigger input pin seg29 lcd controller/driver segment output
mb90925 series 8 (continued) pin no. pin name i/o circuit type* 3 function lqfp* 1 qfp* 2 89 91 p06 e general-purpose input/output port ppg0 16-bit ppg ch.0 output pin tot1 16-bit reload timer ch.1 tot output pin seg30 lcd controller/driver segment output 90 92 p07 e general-purpose input/output port ppg1 16-bit ppg ch.1 output pin tin1 16-bit reload timer ch.1 tin output pin seg31 lcd controller/driver segment output 91 93 p10 g general-purpose input/output port ppg2 16-bit ppg ch.2 output pin 92 94 p11 g general-purpose input/output port tot0 16-bit reload timer ch.0 tot output pin 93 95 p12 g general-purpose input/output port tin0 16-bit reload timer ch.0 tin output pin in3 input capture ch.3 trigger input pin 94 to 96 96 to 98 p13 to p15 g general-purpose input/output port in2 to in0 input capture ch.2 to ch.0 trigger input pins 97 to 100 99, 100, 1, 2 com0 to com3 i lcd controller/driver common output pins 1 to 6 3 to 8 p22 to p27 e general-purpose input/output ports seg0 to seg5 lcd controller/driver segment output pins 7, 8, 10 to 15 9, 10, 12 to 17 p30 to p37 e general-purpose input/output port seg6 to seg13 lcd controller/driver segment output pins 16 to 20, 22 to 24 18 to 22, 24 to 26 p40 to p47 e general-purpose input/output port seg14 to seg21 lcd controller/driver segment output pins 26, 27 28, 29 p90, p91 e general-purpose input/output port seg22, seg23 lcd controller/driver segment output pins 34 36 p50 g general-purpose input/output port int0 int0 external interrupt input pin adtg a/d converter external trigger input pin
mb90925 series 9 (continued) pin no. pin name i/o circuit type* 3 function lqfp* 1 qfp* 2 36 to 39, 41 to 44 38 to 41, 43 to 46 p60 to p67 f general-purpose input/output port an0 to an7 a/d converter input pins 45 47 p51 k general-purpose input/output port int1 int1 external interrupt input pin si sio data input pin 46 48 p52 g general-purpose input/output port int2 int2 external interrupt input pin so sio data output pin 50 52 p53 g general-purpose input/output port int3 int3 external interrupt input pin sck sio clock input/output pin 52 to 55 54 to 57 p70 to p73 h general-purpose input/output port pwm1p0, pwm1m0, pwm2p0, pwm2m0 stepping motor controller ch.0 output pins 57 to 60 59 to 62 p74 to p77 h general-purpose input/output port pwm1p1, pwm1m1, pwm2p1, pwm2m1 stepping motor controller ch.1 output pins 62 to 65 64 to 67 p80 to p83 h general-purpose input/output port pwm1p2, pwm1m2, pwm2p2, pwm2m2 stepping motor controller ch.2 output pins 67 to 70 69 to 72 p84 to p87 h general-purpose input/output port pwm1p3, pwm1m3, pwm2p3, pwm2m3 stepping motor controller ch.3 output pins 72 74 p54 g general-purpose input/output port tx0 can interface 0 tx output pin 73 75 p55 g general-purpose output port rx0 can interface 0 rx input pin
mb90925 series 10 (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 *3: for the i/o circuit type, refer to ? i/o circuit type? *4: type c in mb90f927 and mb90f927s, ty pe d in mb90v925-101 and mb90v925-102. pin no. pin name i/o circuit type* 3 function lqfp* 1 qfp* 2 74 76 p56 g general-purpose input/output port sgo sound generator sgo output pin frck free-run timer clock input pin 76 78 p57 g general-purpose input/output port sga sound generator sga output pin 28 to 31 30 to 33 v0 to v3 ? lcd controller /driver reference power supply pins 56, 66 58, 68 dv cc ? power supply input pins dedicated for high current output buffer (pin numbers 54 to 57, 59 to 62, 64 to 67, 69 to 72) . 51, 61, 71 53, 63, 73 dv ss ? power supply gnd pins dedicated for high current output buffer (pin numbers 54 to 57, 59 to 62 , 64 to 67, 69 to 72) . 32 34 av cc ? a/d converter dedicated power supply input pin 35 37 av ss ? a/d converter dedicated power supply gnd pin 33 35 avrh ? a/d converter vref + input pin 47, 48 49, 50 md0, md1 c test mode input pins. connect to v cc . 49 51 md2 c/d *4 test mode input pin. connect to v ss . 25 27 c ? external capacitor pin. connect an 0.1 f capacitor between this pin and v ss . 21, 82 23, 84 v cc ? power supply input pins 9, 40, 79 11, 42, 81 v ss ? power supply gnd pins
mb90925 series 11 i/o circuit type (continued) type circuit remarks a ? high-speed oscillation pin oscillation feedback resistance : approx. 1 m ? (x0, x1 : main) ? low-speed oscillation pin oscillation feedback resistance : approx. 10 m ? (x0a, x1a : sub) b input dedicated pin (with pull-up resis- tance) pull-up resistance attached : approx. 50 k ? hysteresis input (v ih /v il = 0.8v cc /0.2v cc ) c input dedicated pin hysteresis input (v ih /v il = 0.8v cc /0.2v cc ) d input dedicated pin (with pull-down re- sistance) pull-down resistance attached : approx. 50 k ? hysteresis input (v ih /v il = 0.8v cc /0.2v cc ) e lcdc output common general- purpose port cmos output (i oh /i ol = 4 ma) hysteresis input (v ih /v il = 0.8v cc /0.2v cc ) automotive input (v ih /v il = 0.8v cc /0.5v cc ) x1 x0 xo u t standby control signal hysteresis input hysteresis input hysteresis input p-ch n-ch standby control signal or lcdc output switching signal lcdc output hysteresis input standby control signal or lcdc output switching signal automotive input pout nout
mb90925 series 12 (continued) type circuit remarks f a/d converter input common general- purpose port cmos output (i oh /i ol = 4 ma) hysteresis input (v ih /v il = 0.8v cc /0.2v cc ) automotive input (v ih /v il = 0.8v cc /0.5v cc ) g general-purpose port cmos output (i oh /i ol = 4 ma) hysteresis input (v ih /v il = 0.8v cc /0.2v cc ) automotive input (v ih /v il = 0.8v cc /0.5v cc ) h high current output common general- purpose port cmos output (i oh /i ol = 30 ma) hysteresis input (v ih /v il = 0.8v cc /0.2v cc ) automotive input (v ih /v il = 0.8v cc /0.5v cc ) p-ch n-ch standby control signal or analog input enable signal analog input hysteresis input standby control signal or analog input enable signal automotive input pout nout p-ch n-ch standby control signal hysteresis input standby control signal automotive input pout nout p-ch n-ch standby control signal hysteresis input standby control signal automotive input pout high current output nout high current output
mb90925 series 13 (continued) type circuit remarks i lcdc output pin (com pin) j lcdc output common general- purpose port (serial input) cmos output (i oh /i ol = 4 ma) hysteresis input (v ih /v il = 0.8v cc /0.2v cc ) cmos input (sin) (v ih /v il = 0.7v cc /0.3v cc ) automotive input (v ih /v il = 0.8v cc /0.5v cc ) k general-purpose port (serial input) cmos output (i oh /i ol = 4 ma) hysteresis input (v ih /v il = 0.8v cc /0.2v cc ) cmos input (sin) (v ih /v il = 0.7v cc /0.3v cc ) automotive input (v ih /v il = 0.8v cc /0.5v cc ) n-ch p-ch lcdc output p-ch n-ch standby control signal or lcdc output enable signal lcdc output hysteresis input standby control signal or lcdc output enable signal automotive input standby control signal or lcdc output enable signal cmos input (sin) pout nout p-ch n-ch standby control signal hysteresis input standby control signal automotive input standby control signal cmos input (sin) pout nout
mb90925 series 14 handling devices ? strictly observe maximum rated voltages (preventing latch-up) in cmos ic devices, a condition known as la tch-up may occur if voltages higher than v cc or lower than v ss are applied to input or output pins othe r than medium-or high-voltage pins, or if the voltage applied between v cc and v ss exceeds the rated voltage level. in a latch-up condition, the power supply current can increase dramatically and may destroy semiconductor elements. in using semicondu ctor devices, always take sufficient care to avoid exceeding maximum ratings. also care must be taken when the analog system power supply is switched on or off to ensure that the analog power supply (av cc , avrh) , the analog input voltages and the power supply voltage for the high current output buffer pins (dv cc ) do not exceed the digita l power supply voltage (v cc ) . once the digital power supply voltage (v cc ) has been disconnected, t he analog power supply (av cc , avrh) and the power supply voltage for the high current output buffer pins (dv cc ) may be turned on in any sequence. stable supply voltage even within the warranted operating range of v cc power supply voltage, rapid fl uctuations in the power supply voltage can cause malfunctions. the re commended stability for ripple fluctuations (p-p value) at commercial frequencies (50 hz/60 hz) should be within 10 % of the standard v cc value, and voltage fluctuations that occur during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 v/ms or less. notes on energization power-on procedures in order to prevent the built-in step-down circuits from malfunctioning, the voltage rising time (0.2 v to 2.7 v) during power-on should be attained within 50 s. treatment of unused pins if unused input pins are left open, they may cause ma lfunctions or latch-up which may lead to permanent damage to the semiconductor. unused input pins should therefore be pulled up or pulled down through a resistor of at least 2 k ? . any unused input/output pins should be left open in output status, or if found set to input status, they should be treated in the same way as input pins. treatment of a/d converter power supply pins even if the a/d converter is not used, pins should be connected so that av cc = v cc , and av ss = avrh = v ss . notes on using an external clock even when an external clock is used, an oscillation stab ilization wait time is required following power-on reset or release from sub clock mode or stop mode. also, when an external clock is used, it should drive only the x0 pin and the x1 pin should be left open, as shown below. x0 x1 open mb90925 series sample external clock connection
mb90925 series 15 power supply pins devices are designed to prevent problems such as latch-up when multiple v cc and v ss pins are used, by providing internal connections between pins havi ng the same potential. however, in order to reduce unwanted radiation, to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current ratings, all v cc and v ss pins should always be connected externally to power supplies and ground respectively. as shown in the figure below, all v cc pins must have the same potential and all v ss pins must be at the same potential. if there are multiple v cc or v ss systems, the device will not operate properly even within the warranted operating range. in addition, care must be given to connecting the v cc and v ss pins of this device to the current supply source with as low impedance as possible . it is recommended that a 1.0 f bypass capacitor be connected between the v cc and v ss pins as close to the pins as possible. turning-on sequence of power suppl y to a/d converter and analog inputs the a/d converter power supply (av cc , avrh) and analog inputs (an0 to an7) must be applied after the digital power supply (v cc ) is switched on. when power is shut off, t he a/d converter power supply and analog inputs must be cut off before the digital power supply is switched off (v cc ) . in both power-on a nd power-off, care should be taken that avrh does not exceed av cc . even when pins which double as a nalog input pins are used as input ports, be sure that the i nput voltage does not exceed av cc . handling the power supply for high-current output buffer pins (dv cc , dv ss ) always apply power supply to high -current output buffer pins (dv cc , dv ss ) after the digital power supply (v cc ) is turned on. also when switching the power off, always s hut off the power supply to the high-current output buffer pins (dv cc , dv ss ) before switching off the digital power supply (v cc ) . there is no problem if the high-current output buffer pins and digital power supplie s are turned off and on at the same time. even when the high-current output buffer pins are us ed as general-purpose ports, the power supply for high current output buffer pins (dv cc , dv ss ) should be applied to these pins. pull-up/pull-down resistor mb90925 series does not support inter nal pull-up/pull-down resistor. if necessary, use external components. v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss power supply input pins (v cc /v ss )
mb90925 series 16 precautions for when not using a sub clock signal if the x0a and x1a pins are not connected to an oscilla tor, apply pull-down treatment to the x0a pin and leave the x1a pin open. notes on operation when external clock is stopped when there is no external oscillator or external clock input is stopped, performanc e of the operation by mb90925 series the internal oscillation circuit cannot be guaranteed.
mb90925 series 17 block diagram x0, x1 p92/x0a p93/x1a rst p57/sga p56/sgo/frck p55/rx0 p54/tx0 p53/int3/sck p52/int2/so p51/int1/si p50/int0/adtg p87/pwm2m3 p86/pwm2p3 p85/pwm1m3 p84/pwm1p3 p83/pwm2m2 p82/pwm2p2 p81/pwm1m2 p80/pwm1p2 p77/pwm2m1 p76/pwm2p1 p75/pwm1m1 p74/pwm1p1 p73/pwm2m0 p72/pwm2p0 p71/pwm1m0 p70/pwm1p0 p67 to p60/ an7 to an0 av cc /av ss avrh p91, p90/ seg23, seg22 p47 to p40/ seg21 to seg14 p37 to p30/ seg13 to seg6 com3 to com0 v3 to v0 p00/sin0/int4/seg24 p01/sot0/int5/seg25 p02/sck0/int6/seg26 p03/sin1/int7/seg27 p04/sot1/seg28 p05/sck1/trg/seg29 p06/ppg0/tot1/seg30 p07/ppg1/tin1/seg31 p10/ppg2 p11/tot0 p12/tin0/in3 p13/in2 p14/in1 p15/in0 ram 4 kbytes* rom 64 kbytes* uart0/1 icu0/1/2/3 ppg0/1/2 f 2 mc-16lx bus clock control circuit cpu f 2 mc-16lx core interrupt controller sound generator can controller prescaler 0/1 reload timer 0/1 real-time watch timer free-run timer external interrupt (8 channels) port 8 port 7 port 6 port 9 port 4 port 3 port 5 port 0 port f stepping motor controller 0/1/2/3 a/d converter (8 channels) lcd controller/ driver * : evaluation device (mb90v925-101/102) no built-in rom built-in ram is 6 kbytes. port 2 p27 to p22/ seg5 to seg0 prescaler (sio) sio low voltage/ cpu operation detection reset
mb90925 series 18 memory map note : to select models without the rom mirror function, refer to the ?rom mirror function selection module? in hardware manual. the image of the rom data in the ff bank appears at the top of the 00 bank, in order to enable efficient use of small c compiler models. th e lower 16-bit address for the ff bank will be assigned to the same address, so that tables in rom can be referenced without declaring a ?far? indication with the pointer. for example when accessing the address 00c000 h , the actual access is to address ffc000 h in rom. here the ff bank rom area exceeds 48 kbytes, so that it is not possible to see the entire area in the 00 bank image. therefore becaus e the rom data from ff4000 h to ffffff h will appear in the image from 004000 h to 00ffff h , it is recommended that th e rom data table be stored in the area from ff4000 h to ffffff h . 000000 h 0000d0 h 000100 h address #2 address #1 003900 h 004000 h 010000 h ffffff h single chip mode (with rom mirror function) peripheral area rom area (ff bank image) register rom area ram area peripheral area : internal access memor y : access prohibited part number address #1 address #2 mb90f927/mb90f927s ff0000 h 001100 h mb90v925-101/mb90v925-102 f80000 h 003700 h
mb90925 series 19 i/o map other than can interface (continued) address register name symbol read/write resource name initial value 000000 h port 0 data register pdr0 r/w port 0 x x x x x x x x b 000001 h port 1 data register pdr1 r/w port 1 - - xx x xx x b 000002 h port 2 data register pdr2 r/w port 2 x x x x x x - - b 000003 h port 3 data register pdr3 r/w port 3 x x x x x x x x b 000004 h port 4 data register pdr4 r/w port 4 x x x x x x x x b 000005 h port 5 data register pdr5 r/w port 5 x x x x x x x x b 000006 h port 6 data register pdr6 r/w port 6 x x x x x x x x b 000007 h port 7 data register pdr7 r/w port 7 x x x x x x x x b 000008 h port 8 data register pdr8 r/w port 8 x x x x x x x x b 000009 h port 9 data register pdr9 r/w port 9 - - - - x x x x b 00000a h to 00000f h (disabled) 000010 h port 0 direction register ddr0 r/w port 0 0 0 0 0 0 0 0 0 b 000011 h port 1 direction register ddr1 r/w port 1 - - 0 0 0 0 0 0 b 000012 h port 2 direction register ddr2 r/w port 2 0 0 0 0 0 0 - - b * 000013 h port 3 direction register ddr3 r/w port 3 0 0 0 0 0 0 0 0 b * 000014 h port 4 direction register ddr4 r/w port 4 0 0 0 0 0 0 0 0 b 000015 h port 5 direction register ddr5 r/w port 5 0 0 0 0 0 0 0 0 b 000016 h port 6 direction register ddr6 r/w port 6 0 0 0 0 0 0 0 0 b 000017 h port 7 direction register ddr7 r/w port 7 0 0 0 0 0 0 0 0 b 000018 h port 8 direction register ddr8 r/w port 8 0 0 0 0 0 0 0 0 b 000019 h port 9 direction register ddr9 r/w port 9 - - - - 0 0 0 0 b 00001a h analog input enable ader r/w port 6, a/d 1 1 1 1 1 1 1 1 b 00001b h to 00001f h (disabled) 000020 h a/d control status register lower adcs0 r/w 8/10-bit a/d converter 0 0 0 - - - - 0 b 000021 h a/d control status register higher adcs1 r/w 0 0 0 0 0 0 0 - b 000022 h a/d data register lower adcr0 r 0 0 0 0 0 0 0 0 b 000023 h a/d data register higher adcr1 r - - - - - - 0 0 b 000024 h compare clear register cpclr r/w 16-bit free-run timer xxxxxxxx b 000025 h r/w xxxxxxxx b 000026 h timer data register tcdt r/w 0 0 0 0 0 0 0 0 b 000027 h r/w 0 0 0 0 0 0 0 0 b 000028 h timer control status register lower tccsl r/w 0 0 0 0 0 0 0 0 b 000029 h timer control status register higher tccsh r/w 0 1 - 0 0 0 0 0 b
mb90925 series 20 (continued) address register name symbol read/write resource name initial value 00002a h ppg0 control status register lower pcntl0 r/w 16-bit ppg0 0 0 0 0 0 0 0 0 b 00002b h ppg0 control status register higher pcnth0 r/w 0 0 0 0 0 0 0 1 b 00002c h ppg1 control status register lower pcntl1 r/w 16-bit ppg1 0 0 0 0 0 0 0 0 b 00002d h ppg1 control status register higher pcnth1 r/w 0 0 0 0 0 0 0 1 b 00002e h ppg2 control status register lower pcntl2 r/w 16-bit ppg2 0 0 0 0 0 0 0 0 b 00002f h ppg2 control status register higher pcnth2 r/w 0 0 0 0 0 0 0 1 b 000030 h external interrupt enable enir r/w external interrupt 0 0 0 0 0 0 0 0 b 000031 h external interrupt request eirr r/w 0 0 0 0 0 0 0 0 b 000032 h external interrupt level lower elvrl r/w 0 0 0 0 0 0 0 0 b 000033 h external interrupt level higher elvrh r/w 0 0 0 0 0 0 0 0 b 000034 h serial mode register 0 smr0 r/w uart(lin/sci) 0 0 0 0 0 0 0 0 0 b 000035 h serial control register 0 scr0 r/w 0 0 0 0 0 0 0 0 b 000036 h reception/transmission data register 0 rdr0/ tdr0 r/w 0 0 0 0 0 0 0 0 b 000037 h serial status register 0 ssr0 r/w 0 0 0 0 1 0 0 0 b 000038 h extended communication control register 0 eccr0 r/w 0 0 0 0 0 0 x x b 000039 h extended status control register escr0 r/w 0 0 0 0 0 1 0 0 b 00003a h baud rate generator register 00 bgr00 r/w 0 0 0 0 0 0 0 0 b 00003b h baud rate generator register 01 bgr01 r/w 0 0 0 0 0 0 0 0 b 00003c h , 00003d h (disabled) 00003e h can wake-up control register cwucr r/w can - - - - - - - 0 b 00003f h (disabled) 000040 h to 00004f h area reserved for can interface 0 000050 h timer control status register 0 lower tmcsr0l r/w 16-bit reload timer 0 0 0 0 0 0 0 0 0 b 000051 h timer control status register 0 higher tmcsr0h r/w - - 1 0 0 0 0 0 b 000052 h timer register 0/reload register 0 tmr0/ tmrlr0 r/w xxxxxxxx b 000053 h xxxxxxxx b 000054 h timer control status register 1 lower tmcsr1l r/w 16-bit reload timer 1 0 0 0 0 0 0 0 0 b 000055 h timer control status register 1 higher tmcsr1h r/w - - 1 0 0 0 0 0 b 000056 h timer register 1/reload register 1 tmr1/ tmrlr1 r/w xxxxxxxx b 000057 h xxxxxxxx b
mb90925 series 21 (continued) address register name symbol read/write resource name initial value 000058 h lcd output control register 1 locr1 r/w lcd 1 1 1 1 1 1 1 1 b 000059 h lcd output control register 2 locr2 r/w 0 0 0 0 0 0 0 0 b 00005a h sound control register lower sgcrl r/w sound generator 0 0 0 0 0 0 0 0 b 00005b h sound control register higher sgcrh r/w 0 - - - - 1 0 0 b 00005c h frequency data register sgfr r/w x x x x x x x x b 00005d h amplitude data register sgar r/w 0 0 0 0 0 0 0 0 b 00005e h decrement grade register sgdr r/w x x x x x x x x b 00005f h tone count register sgtr r/w x x x x x x x x b 000060 h input capture register 0 ipcp0 r input capture 0/1 xxxxxxxx b 000061 h xxxxxxxx b 000062 h input capture register 1 ipcp1 r xxxxxxxx b 000063 h xxxxxxxx b 000064 h input capture register 2 ipcp2 r input capture 2/3 xxxxxxxx b 000065 h xxxxxxxx b 000066 h input capture register 3 ipcp3 r xxxxxxxx b 000067 h xxxxxxxx b 000068 h input capture control status 0/1 ics01 r/w input capture 0/1 0 0 0 0 0 0 0 0 b 000069 h input capture edge register 0/1 ice01 r/w input capture 0/1 x x x 0 x 0 x x b 00006a h input capture control status 2/3 ics23 r/w input capture 2/3 0 0 0 0 0 0 0 0 b 00006b h input capture edge register 2/3 ice23 r/w input capture 2/3 x x x x x x x x b 00006c h lcd control register lower lcrl r/w lcd controller/ driver 0 0 0 1 0 0 0 0 b 00006d h lcd control register higher lcrh r/w 0 0 0 0 0 0 0 0 b 00006e h low voltage/cpu operation detection reset control register lvrc r/w low voltage/cpu opera- tion detection reset 0 0 1 1 1 0 0 0 b 00006f h rom mirror romm w rom mirror xxxxxxx1 b 000070 h to 00007f h (disabled) 000080 h pwm control register 0 pwc0 r/w stepping motor controller 0 0 0 0 0 0 - - 0 b 000081 h (disabled) 000082 h pwm control register 1 pwc1 r/w stepping motor controller 1 0 0 0 0 0 - - 0 b 000083 h (disabled) 000084 h pwm control register 2 pwc2 r/w stepping motor controller 2 0 0 0 0 0 - - 0 b 000085 h (disabled) 000086 h pwm control register 3 pwc3 r/w stepping motor controller 3 0 0 0 0 0 - - 0 b
mb90925 series 22 (continued) address register name symbol read/write resource name initial value 000087 h to 000089 h (disabled) 00008a h a/d setting register 0 adsr0 r/w a/d 0 0 0 0 0 0 0 0 b 00008b h a/d setting register 1 adsr1 r/w 0 0 0 0 0 0 0 0 b 00008c h port input level select 0 pil0 r/w port input level select 0 0 0 0 0 0 0 0 b 00008d h port input level select 1 pil1 r/w - - - 0 0 0 0 0 b 00008e h to 00009d h (disabled) 00009e h rom correction control register pacsr r/w address match detection function - - - - - 0 - 0 b 00009f h delay interrupt/release dirr r/w delay interrupt - - - - - - - 0 b 0000a0 h power saving mode lpmcr r/w power saving control circuit 0 0 0 1 1 0 0 0 b 0000a1 h clock select ckscr r/w 1 1 1 1 1 1 0 0 b 0000a2 h to 0000a7 h (disabled) 0000a8 h watchdog control wdtc r/w watchdog timer x x x x x 1 1 1 b 0000a9 h time-base timer control regis- ter tbtc r/w time-base timer 1 - - 0 0 1 0 0 b 0000aa h watch timer control register wtc r/w watch timer (sub clock) 1 x 0 0 0 0 0 0 b 0000ab h to 0000ad h (disabled) 0000ae h flash control register fmcs r/w flash memory interface 0 0 0 x 0 xx 0 b 0000af h (disabled) 0000b0 h interrupt control register 00 icr00 r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000b1 h interrupt control register 01 icr01 r/w 0 0 0 0 0 1 1 1 b 0000b2 h interrupt control register 02 icr02 r/w 0 0 0 0 0 1 1 1 b 0000b3 h interrupt control register 03 icr03 r/w 0 0 0 0 0 1 1 1 b 0000b4 h interrupt control register 04 icr04 r/w 0 0 0 0 0 1 1 1 b 0000b5 h interrupt control register 05 icr05 r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000b6 h interrupt control register 06 icr06 r/w 0 0 0 0 0 1 1 1 b 0000b7 h interrupt control register 07 icr07 r/w 0 0 0 0 0 1 1 1 b 0000b8 h interrupt control register 08 icr08 r/w 0 0 0 0 0 1 1 1 b 0000b9 h interrupt control register 09 icr09 r/w 0 0 0 0 0 1 1 1 b 0000ba h interrupt control register 10 icr10 r/w 0 0 0 0 0 1 1 1 b 0000bb h interrupt control register 11 icr11 r/w 0 0 0 0 0 1 1 1 b 0000bc h interrupt control register 12 icr12 r/w 0 0 0 0 0 1 1 1 b
mb90925 series 23 (continued) address register name symbol read/write resource name initial value 0000bd h interrupt control register 13 icr13 r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000be h interrupt control register 14 icr14 r/w 0 0 0 0 0 1 1 1 b 0000bf h interrupt control register 15 icr15 r/w 0 0 0 0 0 1 1 1 b 0000c0 h serial mode control register (lower) smcsl r/w sio - - - - 0 0 0 0 b 0000c1 h serial mode control register (higher) smcsh r/w 0 0 0 0 0 0 1 0 b 0000c2 h serial data register sdr r/w x x x x x x x x b 0000c3 h communication prescaler control register sdcr r/w communication prescaler (sio) 0 - - - 0 0 0 0 b 0000c4 h serial mode register 1 smr1 r/w uart(lin/sci) 1 0 0 0 0 0 0 0 0 b 0000c5 h serial control register 1 scr1 r/w 0 0 0 0 0 0 0 0 b 0000c6 h reception/transmission data register 1 rdr1/ tdr1 r/w 0 0 0 0 0 0 0 0 b 0000c7 h serial status register 1 ssr1 r/w 0 0 0 0 1 0 0 0 b 0000c8 h extended communication control register 1 eccr1 r/w 0 0 0 0 0 0 x x b 0000c9 h extended status control register 1 escr1 r/w 0 0 0 0 0 1 0 0 b 0000ca h baud rate generator register 10 bgr10 r/w 0 0 0 0 0 0 0 0 b 0000cb h baud rate generator register 11 bgr11 r/w 0 0 0 0 0 0 0 0 b 0000cc h watch timer control register lower wtcrl r/w real-time watch timer 0 0 0 - - 0 0 0 b 0000cd h watch timer control register middle wtcrm r/w 0 0 0 0 0 0 0 0 b 0000ce h watch timer control register higher wtcrh r/w - - - - 0 0 0 0 b 0000cf h sub clock control register sccr w sub clock - - - - 0 0 0 0 b 0000d0 h to 0000ff h (disabled) 001ff0 h rom correction address 0 padr0 r/w address match detection function xxxxxxxx b 001ff1 h rom correction address 1 padr0 r/w x x x x x x x x b 001ff2 h rom correction address 2 padr0 r/w x x x x x x x x b 001ff3 h rom correction address 3 padr1 r/w address match detection function xxxxxxxx b 001ff4 h rom correction address 4 padr1 r/w x x x x x x x x b 001ff5 h rom correction address 5 padr1 r/w x x x x x x x x b 003900 h to 00391f h (disabled) 003920 h ppg0 down counter register pdcr0 r 16-bit ppg 0 1 1 1 1 1 1 1 1 b 003921 h 1 1 1 1 1 1 1 1 b 003922 h ppg0 cycle setting register pcsr0 w xxxxxxxx b 003923 h xxxxxxxx b 003924 h ppg0 duty setting register pdut0 w xxxxxxxx b 003925 h xxxxxxxx b
mb90925 series 24 (continued) address register name symbol read/write resource name initial value 003926 h , 003927 h (disabled) 003928 h ppg1 down counter register pdcr1 r 16-bit ppg 1 1 1 1 1 1 1 1 1 b 003929 h 1 1 1 1 1 1 1 1 b 00392a h ppg1 cycle setting register pcsr1 w xxxxxxxx b 00392b h xxxxxxxx b 00392c h ppg1 duty setting register pdut1 w xxxxxxxx b 00392d h xxxxxxxx b 00392e h , 00392f h (disabled) 003930 h ppg2 down counter register pdcr2 r 16-bit ppg 2 1 1 1 1 1 1 1 1 b 003931 h 1 1 1 1 1 1 1 1 b 003932 h ppg2 cycle setting register pcsr2 w xxxxxxxx b 003933 h xxxxxxxx b 003934 h ppg2 duty setting register pdut2 w xxxxxxxx b 003935 h xxxxxxxx b 003936 h to 003957 h (disabled) 003958 h sub second data register wtbr r/w real time watch timer xxxxxxxx b 003959 h xxxxxxxx b 00395a h - - - xxxxx b 00395b h second data register wtsr r/w - - 0 0 0 0 0 0 b 00395c h minute data register wtmr r/w - - 0 0 0 0 0 0 b 00395d h hour data register wthr r/w - - - 0 0 0 0 0 b 00395e h day data register wtdr r/w 0 0 - 0 0 0 0 1 b 00395f h (disabled) 003960 h to 00396f h lcd display ram vram r/w lcd controller/ driver xxxxxxxx b 003970 h to 00397f h (disabled) 003980 h pwm1 compare register 0 pwc10 r/w stepping motor controller 0 xxxxxxxx b 003981 h - - - - - - xx b 003982 h pwm2 compare register 0 pwc20 r/w xxxxxxxx b 003983 h - - - - - - xx b 003984 h pwm1 select register 0 pws10 r/w - - 0 0 0 0 0 0 b 003985 h pwm2 select register 0 pws20 r/w - 0 0 0 0 0 0 0 b
mb90925 series 25 (continued) address register name symbol read/write resource name initial value 003986 h , 003987 h (disabled) 003988 h pwm1 compare register 1 pwc11 r/w stepping motor controller 1 xxxxxxxx b 003989 h - - - - - - xx b 00398a h pwm2 compare register 1 pwc21 r/w xxxxxxxx b 00398b h - - - - - - xx b 00398c h pwm1 select register 1 pws11 r/w - - 0 0 0 0 0 0 b 00398d h pwm2 select register 1 pws21 r/w - 0 0 0 0 0 0 0 b 00398e h , 00398f h (disabled) 003990 h pwm1 compare register 2 pwc12 r/w stepping motor controller 2 xxxxxxxx b 003991 h - - - - - - xx b 003992 h pwm2 compare register 2 pwc22 r/w xxxxxxxx b 003993 h - - - - - - xx b 003994 h pwm1 select register 2 pws12 r/w - - 0 0 0 0 0 0 b 003995 h pwm2 select register 2 pws22 r/w - 0 0 0 0 0 0 0 b 003996 h , 003997 h (disabled) 003998 h pwm1 compare register 3 pwc13 r/w stepping motor controller 3 xxxxxxxx b 003999 h - - - - - - xx b 00399a h pwm2 compare register 3 pwc23 r/w xxxxxxxx b 00399b h - - - - - - xx b 00399c h pwm1 select register 3 pws13 r/w - - 0 0 0 0 0 0 b 00399d h pwm2 select register 3 pws23 r/w - 0 0 0 0 0 0 0 b 00399e h to 0039ff h (disabled) 003a00 h to 003aff h area reserved for can interface 0 003b00 h to 003bff h (disabled) 003c00 h to 003cff h area reserved for can interface 0 003d00 h to 003eff h (disabled)
mb90925 series 26 (continued) initial value symbols : ?0? : initial value 0 ?1? : initial value 1 ?x? : initial value undetermined ?-? : initial value undetermined (none) write/read symbols : ?r/w? : read/write enabled ?r? : read only ?w? : write only addresses in the area 0000 h to 00ff h are reserved for the principal functions of the mcu. read access attempts to reserved areas will result in an ?x? value. also, write access to reserved areas is prohibited. * : p22/seg0 to p27/seg5 and p30/seg6 to p35/seg 11 initially will be lcd segment output as lcd output control register locr1 (58 h ) is ?11111111 b ? initially. to use port 2 and port 3 as the general-purpose input/ output ports, set locr1 to ?00000000 b ? to disable the lcd segment output first.
mb90925 series 27 can interface (continued) address register name symbol read/ write initial value 000040 h message buffer valid area bvalr r/w 0 0 0 0 0 0 0 0 b 000041 h 0 0 0 0 0 0 0 0 b 000042 h transmission request register treqr r/w 0 0 0 0 0 0 0 0 b 000043 h 0 0 0 0 0 0 0 0 b 000044 h transmission cancel register tcanr w 0 0 0 0 0 0 0 0 b 000045 h 0 0 0 0 0 0 0 0 b 000046 h transmission completed register tcr r/w 0 0 0 0 0 0 0 0 b 000047 h 0 0 0 0 0 0 0 0 b 000048 h receiving completed register rcr r/w 0 0 0 0 0 0 0 0 b 000049 h 0 0 0 0 0 0 0 0 b 00004a h remote request receiving register rrtrr r/w 0 0 0 0 0 0 0 0 b 00004b h 0 0 0 0 0 0 0 0 b 00004c h receiving overrun register rovrr r/w 0 0 0 0 0 0 0 0 b 00004d h 0 0 0 0 0 0 0 0 b 00004e h receiving interrupt enable register rier r/w 0 0 0 0 0 0 0 0 b 00004f h 0 0 0 0 0 0 0 0 b 003c00 h control status register csr r/w, r 0 0 - - - 0 0 0 b 003c01 h 0 - - - - 0 - 1 b 003c02 h last event indicator register leir r/w - - - - - - - - b 003c03 h 0 0 0 - 0 0 0 0 b 003c04 h rx/tx error counter rtec r 0 0 0 0 0 0 0 0 b 003c05 h 0 0 0 0 0 0 0 0 b 003c06 h bit timing register btr r/w - 1 1 1 1 1 1 1 b 003c07 h 1 1 1 1 1 1 1 1 b 003c08 h ide register ider r/w xxxxxxxx b 003c09 h xxxxxxxx b 003c0a h transmission rtr register trtrr r/w 0 0 0 0 0 0 0 0 b 003c0b h 0 0 0 0 0 0 0 0 b 003c0c h remote frame receiving wait register rfwtr r/w xxxxxxxx b 003c0d h xxxxxxxx b 003c0e h transmission interrupt enable register tier r/w 0 0 0 0 0 0 0 0 b 003c0f h 0 0 0 0 0 0 0 0 b
mb90925 series 28 (continued) address register name symbol read/ write initial value 003c10 h acceptance mask select register amsr r/w xxxxxxxx b 003c11 h xxxxxxxx b 003c12 h xxxxxxxx b 003c13 h xxxxxxxx b 003c14 h acceptance mask register 0 amr0 r/w xxxxxxxx b 003c15 h xxxxxxxx b 003c16 h xxxxx- - - b 003c17 h xxxxxxxx b 003c18 h acceptance mask register 1 amr1 r/w xxxxxxxx b 003c19 h xxxxxxxx b 003c1a h xxxxx- - - b 003c1b h xxxxxxxx b 003a00 h to 003a1f h general-purpose ram ? r/w xxxxxxxx b to xxxxxxxx b 003a20 h id register 0 idr0 r/w xxxxxxxx b 003a21 h xxxxxxxx b 003a22 h xxxxx- - - b 003a23 h xxxxxxxx b 003a24 h id register 1 idr1 r/w xxxxxxxx b 003a25 h xxxxxxxx b 003a26 h xxxxx- - - b 003a27 h xxxxxxxx b 003a28 h id register 2 idr2 r/w xxxxxxxx b 003a29 h xxxxxxxx b 003a2a h xxxxx- - - b 003a2b h xxxxxxxx b 003a2c h id register 3 idr3 r/w xxxxxxxx b 003a2d h xxxxxxxx b 003a2e h xxxxx- - - b 003a2f h xxxxxxxx b 003a30 h id register 4 idr4 r/w xxxxxxxx b 003a31 h xxxxxxxx b 003a32 h xxxxx- - - b 003a33 h xxxxxxxx b
mb90925 series 29 (continued) address register name symbol read/ write initial value 003a34 h id register 5 idr5 r/w xxxxxxxx b 003a35 h xxxxxxxx b 003a36 h xxxxx- - - b 003a37 h xxxxxxxx b 003a38 h id register 6 idr6 r/w xxxxxxxx b 003a39 h xxxxxxxx b 003a3a h xxxxx- - - b 003a3b h xxxxxxxx b 003a3c h id register 7 idr7 r/w xxxxxxxx b 003a3d h xxxxxxxx b 003a3e h xxxxx- - - b 003a3f h xxxxxxxx b 003a40 h id register 8 idr8 r/w xxxxxxxx b 003a41 h xxxxxxxx b 003a42 h xxxxx- - - b 003a43 h xxxxxxxx b 003a44 h id register 9 idr9 r/w xxxxxxxx b 003a45 h xxxxxxxx b 003a46 h xxxxx- - - b 003a47 h xxxxxxxx b 003a48 h id register 10 idr10 r/w xxxxxxxx b 003a49 h xxxxxxxx b 003a4a h xxxxx- - - b 003a4b h xxxxxxxx b 003a4c h id register 11 idr11 r/w xxxxxxxx b 003a4d h xxxxxxxx b 003a4e h xxxxx- - - b 003a4f h xxxxxxxx b 003a50 h id register 12 idr12 r/w xxxxxxxx b 003a51 h xxxxxxxx b 003a52 h xxxxx- - - b 003a53 h xxxxxxxx b
mb90925 series 30 (continued) address register name symbol read/ write initial value 003a54 h id register 13 idr13 r/w xxxxxxxx b 003a55 h xxxxxxxx b 003a56 h xxxxx- - - b 003a57 h xxxxxxxx b 003a58 h id register 14 idr14 r/w xxxxxxxx b 003a59 h xxxxxxxx b 003a5a h xxxxx- - - b 003a5b h xxxxxxxx b 003a5c h id register 15 idr15 r/w xxxxxxxx b 003a5d h xxxxxxxx b 003a5e h xxxxx- - - b 003a5f h xxxxxxxx b 003a60 h dlc register 0 dlcr0 r/w - - - -xxxx b 003a61 h - - - -xxxx b 003a62 h dlc register 1 dlcr1 r/w - - - -xxxx b 003a63 h - - - -xxxx b 003a64 h dlc register 2 dlcr2 r/w - - - -xxxx b 003a65 h - - - -xxxx b 003a66 h dlc register 3 dlcr3 r/w - - - -xxxx b 003a67 h - - - -xxxx b 003a68 h dlc register 4 dlcr4 r/w - - - -xxxx b 003a69 h - - - -xxxx b 003a6a h dlc register 5 dlcr5 r/w - - - -xxxx b 003a6b h - - - -xxxx b 003a6c h dlc register 6 dlcr6 r/w - - - -xxxx b 003a6d h - - - -xxxx b 003a6e h dlc register 7 dlcr7 r/w - - - -xxxx b 003a6f h - - - -xxxx b 003a70 h dlc register 8 dlcr8 r/w - - - -xxxx b 003a71 h - - - -xxxx b 003a72 h dlc register 9 dlcr9 r/w - - - -xxxx b 003a73 h - - - -xxxx b 003a74 h dlc register 10 dlcr10 r/w - - - -xxxx b 003a75 h - - - -xxxx b
mb90925 series 31 (continued) address register name symbol read/ write initial value 003a76 h dlc register 11 dlcr11 r/w - - - -xxxx b 003a77 h - - - -xxxx b 003a78 h dlc register 12 dlcr12 r/w - - - -xxxx b 003a79 h - - - -xxxx b 003a7a h dlc register 13 dlcr13 r/w - - - -xxxx b 003a7b h - - - -xxxx b 003a7c h dlc register 14 dlcr14 r/w - - - -xxxx b 003a7d h - - - -xxxx b 003a7e h dlc register 15 dlcr15 r/w - - - -xxxx b 003a7f h - - - -xxxx b 003a80 h to 003a87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx b to xxxxxxxx b 003a88 h to 003a8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx b to xxxxxxxx b 003a90 h to 003a97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx b to xxxxxxxx b 003a98 h to 003a9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx b to xxxxxxxx b 003aa0 h to 003aa7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx b to xxxxxxxx b 003aa8 h to 003aaf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx b to xxxxxxxx b 003ab0 h to 003ab7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx b to xxxxxxxx b 003ab8 h to 003abf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx b to xxxxxxxx b 003ac0 h to 003ac7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx b to xxxxxxxx b 003ac8 h to 003acf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx b to xxxxxxxx b
mb90925 series 32 (continued) address register name symbol read/ write initial value 003ad0 h to 003ad7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx b to xxxxxxxx b 003ad8 h to 003adf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx b to xxxxxxxx b 003ae0 h to 003ae7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx b to xxxxxxxx b 003ae8 h to 003aef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx b to xxxxxxxx b 003af0 h to 003af7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx b to xxxxxxxx b 003af8 h to 003aff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx b to xxxxxxxx b
mb90925 series 33 interrupt sources , interrupt vectors , and interrupt control registers (continued) interrupt source ei 2 os corre- sponding interrupt vector interrupt control register priority * 2 number address icr address reset #08 08 h ffffdc h ?? high int9 instruction #09 09 h ffffd8 h ?? exception processing #10 0a h ffffd4 h ?? can0 rx #11 0b h ffffd0 h icr00 0000b0 h * 1 can0 tx/ns #12 0c h ffffcc h ( reserved) *3 #13 0d h ffffc8 h icr01 0000b1 h * 1 sio *3 #14 0e h ffffc4 h input capture 0 #15 0f h ffffc0 h icr02 0000b2 h * 1 dtp/external interrupt - ch.0 detected #16 10 h ffffbc h reload timer 0 #17 11 h ffffb8 h icr03 0000b3 h * 1 dtp/external interrupt - ch.1 detected #18 12 h ffffb4 h input capture 1 #19 13 h ffffb0 h icr04 0000b4 h * 1 dtp/external interrupt - ch.2 detected #20 14 h ffffac h input capture 2 #21 15 h ffffa8 h icr05 0000b5 h * 1 dtp/external interrupt - ch.3 detected #22 16 h ffffa4 h input capture 3 #23 17 h ffffa0 h icr06 0000b6 h * 1 dtp/external interrupt - ch.4/ch.5 detected #24 18 h ffff9c h ppg timer 0 #25 19 h ffff98 h icr07 0000b7 h * 1 dtp/external interrupt - ch.6/ch.7 detected #26 1a h ffff94 h ppg timer 1 #27 1b h ffff90 h icr08 0000b8 h * 1 reload timer 1 #28 1c h ffff8c h ppg timer 2 #29 1d h ffff88 h icr09 0000b9 h * 1 real time watch timer #30 1e h ffff84 h free-run timer overflow #31 1f h ffff80 h icr10 0000ba h * 1 a/d converter conversion end #32 20 h ffff7c h free-run timer clear #33 21 h ffff78 h icr11 0000bb h * 1 sound generator #34 22 h ffff74 h time-base timer #35 23 h ffff70 h icr12 0000bc h * 1 watchdog (sub clock) #36 24 h ffff6c h uart 1 rx #37 25 h ffff68 h icr13 0000bd h * 1 uart 1 tx #38 26 h ffff64 h uart 0 rx #39 27 h ffff60 h icr14 0000be h * 1 uart 0 tx #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h * 1 delay interrupt generator module #42 2a h ffff54 h low
mb90925 series 34 (continued) : usable, with ei 2 os stop function : usable : usable when interrupt source s sharing icr are not in use : unusable *1 : ? peripheral functions sharing the icr r egister have the same interrupt level. ? if peripheral functions sharing the icr register are using expanded intelligent i/o services, one or the other cannot be used. ? when peripheral functions are sharing the icr register and one specifies expanded intelligent i/o services, the interrupt from the other function cannot be used. *2 : priority applies when interrup ts of the same level are generated. *3 : sio and can1 tx/nx will share irq3 in evaluation chip (mb90v925-101/102) .
mb90925 series 35 electrical characteristics 1. absolute maximum ratings *1 : the parameter is based on v ss = av ss = dv ss = 0.0 v. *2 : av cc , avrh and dv cc shall never exceed v cc . also, avrh shall never exceed av cc . *3 : the maximum current to/from and input are limit ed by some means with external components, the i clamp rating supersedes the vi rating. *4 : maximum output current is define d as the peak value of the current of any one of the corresponding pins. *5 : average output current is defined as the value of the average current flow ing over 100 ms at any one of the corresponding pins. the ?average value? can be calculated from the formula of ?operating current? times ?operating factor?. (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v av cc = v cc * 2 avrh v ss ? 0.3 v ss + 6.0 v av cc avrh* 2 dv cc v ss ? 0.3 v ss + 6.0 v dv cc = v cc * 2 input voltage* 1 v i v ss ? 0.3 v cc + 0.3 v *3 output voltage* 1 v o v ss ? 0.3 v cc + 0.3 v maximum clamp current i clamp ? 400 + 400 a*7 total maximum clamp current | i clamp | ? 4ma*7 ?l? level maximum output current* 4 i ol1 ? 15 ma other than p70 to p77 and p80 to p87 i ol2 ? 40 ma p70 to 77 and p80 to87 ?l? level average output current* 5 i olav1 ? 4 ma other than p70 to p77 and p80 to p87 i olav2 ? 30 ma p70 to 77 and p80 to 87 ?l? level maximum total output current i ol1 ? 100 ma other than p70 to p77 and p80 to p87 i ol2 ? 330 ma p70 to 77 and p80 to 87 ?l? level average total output current i olav1 ? 50 ma other than p70 to p77 and p80 to p87 i olav2 ? 250 ma p70 to 77 and p80 to 87 ?h? level maximum output current i oh1 * 4 ?? 15 ma other than p70 to p77 and p80 to p87 i oh2 * 4 ?? 40 ma p70 to 77 and p80 to 87 ?h? level average output current i ohav1 * 5 ?? 4 ma other than p70 to p77 and p80 to p87 i ohav2 * 5 ?? 30 ma p70 to 77 and p80 to 87 ?h? level maximum total output current i oh1 ?? 100 ma other than p70 to p77 and p80 to p87 i oh2 ?? 330 ma p70 to 77 and p80 to 87 ?h? level average total output current i ohav1 * 6 ?? 50 ma other than p70 to p77 and p80 to p87 i ohav2 * 6 ?? 250 ma p70 to 77 and p80 to 87 power consumption p d ? 500 mw operating temperature t a ? 40 + 105 c storage temperature t stg ? 55 + 150 c
mb90925 series 36 (continued) *6 : average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. the ?average value? can be calculated from the formula of ?operating current? times ? operating factor?. *7 : ? applicable to pins : p10 to p15, p50 to p57, p70 to p77, p80 to p87 ? use within recommended operating conditions. ? use at dc voltage (current) . ? the + b signal should always be applied with a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied, the input current to the microcontroller pin does not exceed rated valu es, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microc ontroller power supply is off (n ot fixed at 0 v) , the power supply is provided from the pins, so t hat incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting power supply voltag e may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pins (lcd dr ive pins, comparator input pins, etc.) cannot accept + b signal input. ? sample recommended circuits : warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r + b input (0 v to 16 v) limiting resistance protective diode input/output equivalent circuits
mb90925 series 37 2. recommended operating conditions (v ss = dv ss = av ss = 0.0 v) * : for smoothing capacitor cs connections, refer to the illustration below. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc av cc dv cc 3.7 5.5 v (mb90f927/mb90f927s) low voltage detection reset starts to work when power supply voltage is 4.0 v 0.3 v. 4.3 5.5 v holding stop operation status (mb90f927/mb90f927s) smoothing capacitor* c s 0.1 1.0 f use a ceramic capacitor or ot her capacitor of equivalent frequency characteristics. a bypass capacitor on the v cc pin should have a capacitance greater than cs. operating temperature t a ? 40 + 105 c c c s v ss dv ss av ss c pin connection diagram
mb90925 series 38 3. dc characteristics (v cc = 5.0 v 10 % , v ss = dv ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (continued) parameter symbol pin name conditions value unit remarks min typ max ?h? level input voltage v iha ? ? 0.8 v cc ? v cc + 0.3 v pin inputs if automotive input levels are selected* 1 v ihs2 ? ? 0.8 v cc ? v cc + 0.3 v pin inputs if cmos hysteresis input levels are selected* 1 (0.8vcc/0.2vcc cmos hysteresis is selected for p00, p03 and p51) v ihs1 ? ? 0.7 v cc ? v cc + 0.3 v pin inputs if 0.7vcc/ 0.3vcc cmos hys- teresis input levels is selected for p00, p03 and p51. v ihr ? ? 0.8 v cc ? v cc + 0.3 v rst input pin (cmos hysteresis) v ihm ? ? v cc ? 0.3 ? v cc + 0.3 v md pin* 2 ?l? level input voltage v ila ? ? v ss ? 0.3 ? 0.5 v cc v pin inputs if automotive input levels are selected* 1 v ils2 ? ? v ss ? 0.3 ? 0.2 v cc v pin inputs if cmos hysteresis input levels are selected* 1 (0.8vcc/0.2vcc cmos hysteresis is selected for p00, p03 and p51) v ils1 ? ? v ss ? 0.3 ? 0.3 v cc v pin inputs if 0.7vcc/ 0.3vcc cmos hys- teresis input levels is selected for p00, p03 and p51. v ilr ? ? v ss ? 0.3 ? 0.2 v cc v rst input pin (cmos hysteresis) v ilm ? ? v ss ? 0.3 ? v ss + 0.3 v md pin* 2
mb90925 series 39 (v cc = 5.0 v 10 % , v ss = dv ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (continued) parameter symbol pin name conditions value unit remarks min typ max power supply current* 3 i cc v cc operating frequency f cp = 16 mhz, normal operation ? 35 45 ma operating frequency f cp = 16 mhz, writing flash memory ? 50 60 ma flash memory product operating frequency f cp = 16 mhz, erasing flash memory ? 50 60 ma i ccs operating frequency f cp = 16 mhz, sleep mode ? 12 20 ma i cts operating frequency f cp = 2 mhz, time-base timer mode ? 0.4 1.0 ma i ctspll operating frequency f cp = 16 mhz, pll timer mode, external frequency = 4mhz ? 47ma i ccl operating frequency f cp = 8 khz, t a = + 25 c, sub clock operation ? 90 200 a i ccls operating frequency f cp = 8 khz, t a = + 25 c, sub sleep operation ? 60 150 a i cct operating frequency f cp = 8 khz, t a = + 25 c, watch mode ? 60 130 a i cch t a = + 25 c, stop mode ? 50 130 a input leakage current i il all input pins v cc = dv cc = av cc = 5.5 v v ss < v i < v cc ? 5 ?+ 5 a input capacitance 1 c in1 other than v cc , v ss , dv cc , dv ss , av cc , av ss , c, p70 to p77, p80 to p87 ?? 515pf
mb90925 series 40 (continued) (v cc = 5.0 v 10 % , v ss = dv ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) *1 : all input pins except x0, x0a, md0, md1, and md2. *2 : md0, md1, and md2 pins. *3 : power supply current values assume external clock feed from the x1 pin and x1a pin. users must be aware that power supply current levels differ dependi ng on whether an external clock or oscillator is used. *4 : defined as maximum variation in v oh2 /v ol2 with all ch.0 pwm1p0/pwm1m0/pwm2p0/pwm2m0 simultaneously on. similarly for other channels. parameter symbol pin name conditions value unit remarks min typ max input capacitance 2 c in2 p70 to p77, p80 to p87 ?? 15 45 pf pull-up resistance r up rst ? 25 50 100 k ? pull-down resistance r down md2 ? 25 50 100 k ? except flash memory product output ?h? voltage 1 v oh1 other than p70 to p77, p80 to p87 v cc = 4.5 v i oh = ? 4.0 ma v cc ? 0.5 ?? v output ?h? voltage 2 v oh2 p70 to p77, p80 to p87 v cc = 4.5 v i oh = ? 30.0 ma v cc ? 0.5 ?? v output ?l? voltage 1 v ol1 other than p70 to p77, p80 to p87 v cc = 4.5 v i ol = 4.0 ma ?? 0.4 v output ?l? voltage 2 v ol2 p70 to p77, p80 to p87 v cc = 4.5 v i ol = 30.0 ma ?? 0.55 v large current output drive capacity variation 1 ? v oh2 pwm1pn, pwm1mn, pwm2pn, pwm2mn, (n = 0 to 3) v cc = 4.5 v i oh = 30.0 ma v oh2 maximum variation 0 ? 90 mv *4 large current output drive capacity variation 2 ? v ol2 pwm1pn, pwm1mn, pwm2pn, pwm2mn, (n = 0 to 3) v cc = 4.5 v i oh = 30.0 ma v ol2 maximum variation 0 ? 90 mv *4 lcd internal divider resistance r lcd v0 to v3 ? 50 100 200 k ? com0 to com3 output impedance r vcom comn (n = 0 to 3) ??? 2.5 k ? seg0 to seg31 output impedance r vseg segn (n = 0 to 31) ??? 15 k ? lcd leakage current i lcdc v0 to v3 comm (m = 0 to 3) segn (n = 0 to 31) ?? 5.0 ?+ 5.0 a
mb90925 series 41 4. ac characteristics (1) clock timing (v cc = 5.0 v 10 % , v ss = dv ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin name condi- tions value unit remarks min typ max base oscillation clock frequency f c x0, x1 ? 4 ? 12 mhz 1/2 (when pll stops) 4 ? 12 mhz pll x 1 4 ? 8 mhz pll x 2 4 ? 5.33 mhz pll x 3 4 ? 4 mhz pll x 4 f lc x0a, x1a ? 32.768 ? khz base oscillation clock cycle time t cyl x0, x1 ? 250 ? ns t lcyl x0a, x1a ? 30.5 ? s input clock pulse width p wh , p wl x0 10 ?? ns use duty ratio of 40 to 60 % as a guideline p wlh , p wll x0a ? 15.2 ? s input clock rise and fall time tcr, tcf x0, x0a ?? 5ns external clock signal internal operating clock frequency f cp ? 2 ? 16 mhz using main clock (pll clock) f lcp ?? 8.192 ? khz using sub clock internal operating clock cycle time t cp ? 62.5 ? 500 ns using main clock (pll clock) t lcp ?? 122.1 ? s using sub clock x0 tcf tcr 0.8 v cc 0.2 v cc p wl t cyl p wh x0a t lcyl tcf tcr 0.8 v cc 0.2 v cc p wlh p wll ? x0 clock timing ? x0a clock timing
mb90925 series 42 ? range of guaranteed operation note : the mb90f927/ mb90f927s enters reset mode at power supply voltage below 4 v 0.3 v. 16 4 2 5.5 3.7 relation between internal operating clock frequency and power supply voltage guaranteed operation range power supply voltage v cc (v) guaranteed pll operation range internal operating clock frequency f cp (mhz) 4.0 guaranteed a/d converter operation range 16 8 16 8 guaranteed oscillation frequency range internal clock fcp (mhz) external clock fc (mhz) 12 2 4 4 12 x 1/2 (pll off) x 1 x 2 x 4 x3
mb90925 series 43 (2) reset input (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) *: oscillator?s oscillation time is the time that the amplitude reaches 90%. th e oscillation time of a crystal oscillator is between several ms and tens of ms. the oscillation time of a ceramic oscillator is between hundreds of s and several ms. the oscillation time of an external clock is 0 ms. parameter symbol pin name value unit remarks min max reset input time t rstl rst 500 ? ns at normal operation oscillator oscillation time* + 100 s ? ms at stop mode, sub clock mode, sub sleep mode, and watch mode 100 ? s at time-base timer mode r s t x0 100 s t r s tl 0.2 vcc 0.2 vcc intern a l oper a tion clock intern a l re s et 90 % of a mplit u de o s cill a tor o s cill a tion time o s cill a tion s t ab iliz a tion w a it time exec u tion of the in s tr u ction at stop mode, sub clock mode, sub sleep mode, watch mode, and power-on rst 0.2 v cc t rstl 0.2 v cc at normal operation
mb90925 series 44 (3) power-on reset (v ss = 0.0 v, t a = ? 40 c to + 105 c) note : extreme variations in power supply voltage may ac tivate a power-on reset. as the illustration below shows, when varying power supply voltage during operation, the use of a smooth volt age rise with suppressed fluctuation is recommended. also in this situation, th e pll clock on the device should not be used, however it is permissible to use the pll clock during a voltage drop of 1v/s or less. parameter symbol pin name conditions value unit remarks min max power supply rise time t r v cc ? 0.05 30 ms power supply start voltage v off ? 0.2 v power supply attained voltage v on 2.7 ? v power supply cutoff time t off 50 ? ms waiting time until power-on v cc t r t off 2.7 v 0.2 v 0.2 v 0.2 v 0 v v cc v ss 5.0 v 3.0 v ram data hold a rise slope of 50 mv/ms or less is recommended
mb90925 series 45 (4) sio timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) notes : ? ac ratings are for clk synchronous mode. ? c l is load capacitance connec ted to pin during testing. ? t cp is internal operating clock cycle time. refer to ? (1) clock timing?. parameter symbol pin name conditions value unit min max serial clock cycle time t scyc sck internal shift clock mode output pin c l = 80 pf + 1ttl 8 t cp ? ns sck so delay time t slov sck, so ? 80 + 80 ns valid si sck t ivsh sck, si 100 ? ns sck valid si hold time t shix 60 ? ns serial clock ?h? pulse width t shsl sck external shift clock mode output pin c l = 80 pf + 1ttl 4 t cp ? ns serial clock ?l? pulse width t slsh 4 t cp ? ns sck so delay time t slov sck, so ? 150 ns valid si sck t ivsh sck, si 60 ? ns sck valid si hold time t shix 60 ? ns internal shift clock mode external shift clock mode sck so si t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.5 v cc 0.8 v cc 0.5 v cc sck so si t slsh t shsl t slov t ivsh t shix 0.5 v cc 0.5 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.5 v cc 0.8 v cc 0.5 v cc
mb90925 series 46 (5) uart0/1 (lin/sci) ? bit setting: escr0/1:sces=0, eccr0/1:scde=0 (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) notes : ? ac characteristic in clk synchronized mode. ? c l is load capacity value of pins when testing. ? t cp is internal operating clock cycle time (machine clock). refer to ? (1) clock timing?. parameter symbol pin name conditions value unit min max serial clock cycle time t scyc sck0, sck1 internal shift clock mode output pins are c l = 80 pf + 1ttl 5 t cp ? ns sck sot delay time t slovi sck0, sck1, sot0, sot1 ? 50 + 50 ns valid sin sck t ivshi sck0, sck1, sin0, sin1 t cp + 80 ? ns sck valid sin hold time t shixi 0 ? ns serial clock ?l? pulse width t slsh sck0, sck1 external shift clock mode output pins are c l = 80 pf + 1ttl t cp + 10 ? ns serial clock ?h? pulse width t shsl 3 t cp ? t r ? ns sck sot delay time t slove sck0, sck1, sot0, sot1 ? 2 t cp + 60 ns valid sin sck t ivshe sck0, sck1, sin0, sin1 30 ? ns sck valid sin hold time t shixe t cp + 30 ? ns sck fall time t f sck0, sck1 ? 10 ns sck rise time t r ? 10 ns
mb90925 series 47 internal shift clock mode external shift clock mode s ck s ot s in t s l s h t s h s l t s love t iv s he t s hixe v il v il v ih v ih 2.4 v 0. 8 v v ih v il v ih v il t f t r v ih s ck s ot s in t s l s h t s h s l t s love t iv s he t s hixe v il v il v ih v ih 2.4 v 0. 8 v v ih v il v ih v il t f t r v ih
mb90925 series 48 ? bit setting: escr0/1:sces=1, eccr0/1:scde=0 (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin name conditions value unit min max serial clock cycle time t scyc sck0, sck1 internal shift clock mode output pins are c l = 80 pf + 1ttl 5 t cp ? ns sck sot delay time t slovi sck0, sck1, sot0, sot1 ? 50 + 50 ns valid sin sck t ivshi sck0, sck1, sin0, sin1 t cp + 80 ? ns sck valid sin hold time t shixi 0 ? ns serial clock ?h? pulse width t shsl sck0, sck1 external shift clock mode output pins are c l = 80 pf + 1ttl 3 t cp ? t r ? ns serial clock ?l? pulse width t slsh t cp + 10 ? ns sck sot delay time t slove sck0, sck1, sot0, sot1 ? 2 t cp + 60 ns valid sin sck t ivshe sck0, sck1, sin0, sin1 30 ? ns sck valid sin hold time t shix t cp + 30 ? ns sck fall time t f sck0, sck1 ? 10 ns sck rise time t r ? 10 ns
mb90925 series 49 internal shift clock mode external shift clock mode s ck s ot s in t s cyc t s hovi t iv s li t s lixi 2.4 v 2.4 v 0. 8 v 2.4 v 0. 8 v v ih v il v ih v il s ck s ot s in t s h s l t s l s h t s hove t iv s le t s lixe v ih v il v ih v il 2.4 v 0. 8 v v ih v il v ih v il t r t f v il
mb90925 series 50 ? bit setting: escr0/1:sces=0, eccr0/1:scde=1 (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) notes : t cp is the machine clock cycle time (unit : ns ) . refer to ? (1) clock timing?rating for t cp . parameter symbol pin name conditions value unit min max serial clock cycle time t scyc sck0, sck1 internal clock operation output pins are c l = 80 pf + 1ttl 5 t cp ? ns sck sot delay time t shovi sck0, sck1, sot0, sot1 ? 50 + 50 ns valid sin sck t ivsli sck0, sck1, sin0, sin1 t cp + 80 ? ns sck valid sin hold time t slixi 0 ? ns sot sck delay time t sovli sck0, sck1, sot0, sot1 3 t cp ? 70 ? ns s ck s ot s in t s hovi t s cyc t s ovli t iv s li t s lixi 0. 8 v 2.4 v 0. 8 v 2.4 v 0. 8 v v ih v il v ih v il 2.4 v 0. 8 v
mb90925 series 51 ? bit setting: escr0/1:sces=1, eccr0/1:scde=1 (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) notes : t cp is the machine clock cycle time (unit : ns ) . refer to ? (1) clock timing?rating for t cp . parameter symbol pin name conditions value unit min max serial clock cycle time t scyc sck0, sck1 internal clock operation output pins are c l = 80 pf + 1ttl 5 t cp ? ns sck sot delay time t slovi sck0, sck1, sot0, sot1 ? 50 + 50 ns valid sin sck t ivshi sck0, sck1, sin0, sin1 t cp + 80 ? ns sck valid sin hold time t shixi 0 ? ns sot sck delay time t sovhi sck0, sck1, sot0, sot1 3 t cp ? 70 ? ns s ck s ot s in t s lovi t s cyc t s ovhi t iv s hi t s hixi 0. 8 v 2.4 v 2.4 v 2.4 v 0. 8 v v ih v il v ih v il 2.4 v 0. 8 v
mb90925 series 52 (6) timer input timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) note : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. parameter symbol pin name conditions value unit min max input pulse width t tiwh t tiwl tin0, tin1, in0 to in3 ? 4 t cp ? ns tin0 , tin1 in0 to in3 v ih v ih v il v il t tiwh t tiwl timer input timing
mb90925 series 53 (7) trigger input timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) note : t cp is internal operating clock cycle time (machine clock) . refer to ? (1) clock timing?. parameter symbol pin name conditions value unit min max input pulse width t trgh , t trgl int0 to int7 ? 200 ? ns adtg ? t cp + 200 ? ns int0 to int7 v ih v ih v il v il t trgh t trgl trigger input timing
mb90925 series 54 (8) low voltage detection (v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min typ max detection voltage v dl v cc ? 3.7 4.0 4.3 v during voltage drop hysteresis width v hys v cc ? 0.1 ?? v during voltage rise power supply voltage fluctuation ratio dv/dt v cc ?? 0.1 ?+ 0.02 v/ s detection delay time t d ???? 35 s v hys dv dt v ni t d v cc t d internal reset
mb90925 series 55 5. a/d converter (1) electrical characteristics (v cc = av cc = 5.0 v 10 % , 3.0v avrh-avss, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) * : defined as supply current (when v cc = av cc = avrh = 5.0 v) with a/d converte r not operating, and cpu in stop mode. parameter symbol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb non-linear error ?? ? ? 2.5 lsb differential linear error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v 1 lsb = (avrh ? av ss ) / 1024 full scale transition voltage v fst an0 to an7 avrh ? 3.5 lsb avrh ? 1.5 lsb avrh + 0.5 lsb v sampling time t smp ? 1.4 ? 16500 s 4.5 v avcc 5.5 v 2.0 4.0 v avcc 4.5 v compare time t cmp ? 0.5 ? ? s 4.5 v avcc 5.5 v 1.2 4.0 v avcc 4.5 v analog port input current i ain an0 to an7 ? 0.3 ? +0.3 a analog input voltage v ain an0 to an7 avss ? avrh v reference voltage avrh avrh avss+2.7 ? av cc v power supply current i a av cc ? 3.5 7.5 ma i ah ?? 5 a* reference voltage supply current i r avrh ? 600 900 av avrh = 5.0 v i rh avrh ?? 5 a* inter-channel variation ? an0 to an7 ?? 4lsb
mb90925 series 56 ? notes of the external impedance of the analog input and its sampling time a/d converter with sample and hold circuit. if the exte rnal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore, to satisfy the a/d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external im pedance so that the sampling time is longer than the minimum value. also, if the sampling time cannot be suffic ient, connect a capacitor of about 0.1 f to the analog input pin. r comp a r a tor c analog input analog input equivalent circuit during sampling : on note : the values are reference values. mb90f927/mb90f927s r c 4.5 v avcc 5.5 v : 2.0 k ? (max) 16.0 pf (max) 4.0 v avcc 4.5 v : 8.2 k ? (max) 16.0 pf (max) mb90v925-101/102 4.5 v avcc 5.5 v : 2.0 k ? (max) 14.4 pf (max) 4.0 v avcc 4.5 v : 8.2 k ? (max) 14.4 pf (max)
mb90925 series 57 ? about errors as | avrh - av ss | becomes smaller, values of relative errors grow larger. 100 90 8 0 70 60 50 40 3 0 20 10 0 0 5 10 15 20 25 3 0 3 5 mb90f927/f927 s mb90v925-101/102 20 18 16 14 12 10 8 6 4 2 0 0123456 8 7 mb90f927/f927s mb90v925-101/102 (external impedance = 0 k ? to 100 k ? ) external impedance [k ? ] minimum sampling time [ s] (external impedance = 0 k ? to 20 k ? ) external impedance [k ? ] minimum sampling time [ s] the relationship between the exter nal impedance and minimum sampling time 20 1 8 16 14 12 10 8 6 4 2 0 012 3 456 8 7 mb90f927/f927 s mb90v925-101/102 (external impedance = 0 k ? to 20 k ? ) external impedance [k ? ] minimum sampling time [ s] 100 90 8 0 70 60 50 40 3 0 20 10 0 0 5 10 15 20 25 3 0 3 5 mb90f927/f927 s mb90v925-101/102 (external impedance = 0 k ? to 100 k ? ) external impedance [k ? ] minimum sampling time [ s] at 4.5 v avcc 5.5 v at 4.0 v avcc 4.5 v
mb90925 series 58 (2) definition of terms resolution : analog changes that ar e identifiable with the a/d converter. non-linear error : the deviation of the stra ight line connecting the zero transition point (?00 0000 0000? ? ?00 0000 0001?) with the full-scale transition point (?11 1111 1110? ? ?11 1111 1111?) from actual conversion characteristics. differential linear error : the deviation of input volt age needed to change the output code by 1 lsb from the ideal value. total error : the total error is defined as a differ ence between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linear error. (continued) total error actual conversion value analog input total error for digital output n = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb(ideal) = avrh ? av ss 1024 [v] v ot (ideal) = avss + 0.5 lsb [v] v fst (ideal) = avrh ? 1.5 lsb [v] v nt : voltage at a transition of digital output from (n - 1) h to n h actual conversion value ideal characteristics (measured value) digital output av ss avrh 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 1.5 lsb v nt {1 lsb x (n - 1) + 0.5 lsb} 0.5 lsb n : a/d converter digital output value
mb90925 series 59 (continued) 6. flash memory program/erase characteristics * : this value comes from the technology qualification. (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) parameter conditions value unit remarks min typ max chip erase time t a = + 25 c v cc = 5.0 v ? 115s excludes pre-programming before erase byte (8-bit width) programming time ? 32 3600 s excludes system-level overhead erase/program cycle ? 10000 ?? cycle flash memory data retention time average t a = + 85 c 20 ?? year * non-linear error digital output differential linear error (measured value) (measured value) non-linear error of digital output n v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] = differential linear error of digital output n v ( n + 1 ) t ? v nt 1 lsb ? 1 [lsb] = v fst ? v ot 1022 [v] 1 lsb = n : a/d converter digital output value v ot : voltage at transition of digital output from ?000 h ? to ?001 h ? v fst : voltage at transition of digital output from ?3fe h ? to ?3ff h ? actual conversion value actual conversion value ideal characteristics digital output analog input analog input actual conversion value {1 lsb x (n -1) + v ot } actual conversion value ideal characteristics (measured value) avss avrh 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h v nt v ot (measured value) v fst (measured value) avss avrh n + 1 h n h n - 1 h n - 2 h v (n + 1)t v nt
mb90925 series 60 ordering information part number package remarks MB90F927PF-GE1 mb90f927spf-ge1 100-pin plastic qfp (fpt-100p-m06) mb90f927pfv-ge1 mb90f927spfv-ge1 100-pin plastic lqfp (fpt-100p-m05) mb90v925-101 mb90v925-102 299-pin ceramic pga (pga-299c-a01) for evaluation
mb90925 series 61 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 100-pin pl as tic qfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 14.00 20.00 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 3 . 3 5 mm max code (reference) p-qfp100-14 20-0.65 100-pin pl as tic qfp (fpt-100p-m06) ( fpt-100p-m06 ) c 2002 fujit s u limited f10000 8s -c-5-5 1 3 0 3 1 50 51 8 0 8 1 100 20.000.20(.7 8 7.00 8 ) 2 3 .900.40(.941.016) 14.000.20 (.551.00 8 ) 17.900.40 (.705.016) index 0.65(.026) 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) "a" 0.170.06 (.007.002) 0.10(.004) det a il s of "a" p a rt (.0 3 5.006) 0. 88 0.15 (.0 3 1.00 8 ) 0. 8 00.20 0.25(.010) 3 .00 +0. 3 5 ?0.20 +.014 ?.00 8 .11 8 (mo u nting height) 0.250.20 (.010.00 8 ) ( s t a nd off) 0~ 8 ? * * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb90925 series 62 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 100-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 14.0 14.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0.65g code (reference) p-lfqfp100-14 14-0.50 100-pin pl as tic lqfp (fpt-100p-m05) (fpt-100p-m05) c 200 3 fujit s u limited f100007 s -c-4-6 14.000.10(.551.004) s q 16.000.20(.6 3 0.00 8 ) s q 125 26 51 76 50 75 100 0.50(.020) 0.200.05 (.00 8 .002) m 0.0 8 (.00 3 ) 0.1450.055 (.0057.0022) 0.0 8 (.00 3 ) "a" index .059 ?.004 +.00 8 ?0.10 +0.20 1.50 (mo u nting height) 0 ? ~ 8 ? 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.25(.010) 0.100.10 (.004.004) det a il s of "a" p a rt ( s t a nd off) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb90925 series f0705 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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